New instruction that intel/amd should add

[Gerd Isenberg]

There was a whole lot more to my proposal than the one simple example that Westcott decided to pick on and was not even the main focus of my idea. The main focus of my idea was a noncintiguous bit sub processor under control of source mask and destination mask. A much bigger waste of silicon!

You mentioned "This would allow simple iteration through all the possible sets (values) of the masked data" and that is excactly what Steffan's algorithms does - traversing all subsets of a set d, starting with the empty set. Did you understand that "simple" algorithm immediatly? It took me quite a while to get the idea of that carry rippler. No reason to become harsh or unrespectful, by calling Steffan by his surname only.

I have no idea what a noncintiguous bit sub processor under control of source mask and destination mask is. Can you please elaborate a bit more about that? E.g. with some sample bit-pattern or in C- or pseudo code.

Thanks,
Gerd

[Michael Sherwin]

There was a whole lot more to my proposal than the one simple example that Westcott decided to pick on and was not even the main focus of my idea. The main focus of my idea was a noncintiguous bit sub processor under control of source mask and destination mask. A much bigger waste of silicon!

You mentioned "This would allow simple iteration through all the possible sets (values) of the masked data" and that is excactly what Steffan's algorithms does - traversing all subsets of a set d, starting with the empty set. Did you understand that "simple" algorithm immediatly? It took me quite a while to get the idea of that carry rippler. No reason to become harsh or unrespectful, by calling Steffan by his surname only.

I have no idea what a noncintiguous bit sub processor under control of source mask and destination mask is. Can you please elaborate a bit more about that? E.g. with some sample bit-pattern or in C- or pseudo code.

Thanks,
Gerd

Hi Gerd,

Here is my original idea. Take the bits that are under a source mask. Those bits could represent, say for example, the blockers of a rook and move them to the positons that are under the destination mask, such that bit 1 of the source mask goes to bit 1 of the destination mask and bit 2 of the source mask goes to bit 2 of the destination mask, etc. This one example would create an index into a rook attack table with one instruction! However, the instruction can be used for a whole lot more. Adding additional ways to act upon the masked data would make it a noncontiguous (non adjacent) bit subprocessor.

Mike

[H.G.Muller]

This would be a very useful instruction, but unimplementable, I am afraid. Not everything that is useful or in high demand can actually be done. You are pretty much asking for a miracle. For ages people like to have a divide instruction, and no one contests its usefulness. But it still takes 36 clocks to do the 64-bit division.
What you now propose has many things in common with division. In particular, what a certain bit does (where it goes) depends on the setting of all lower-order bits in mask1 and mask2. Probably the only way to do it is to cycle through the bits. This means that such an instruction, if they could make it, would take 64 or 32 clocks.

Besides, this instruction would need 3 sources, which conflicts with the design of x86 machines...

We might as well ask for an instruction that takes a board description in two XMM registers, and replaces it with the best move and its score...

[Michael Sherwin]

This would be a very useful instruction, but unimplementable, I am afraid. Not everything that is useful or in high demand can actually be done. You are pretty much asking for a miracle. For ages people like to have a divide instruction, and no one contests its usefulness. But it still takes 36 clocks to do the 64-bit division.
What you now propose has many things in common with division. In particular, what a certain bit does (where it goes) depends on the setting of all lower-order bits in mask1 and mask2. Probably the only way to do it is to cycle through the bits. This means that such an instruction, if they could make it, would take 64 or 32 clocks.

Besides, this instruction would need 3 sources, which conflicts with the design of x86 machines...

We might as well ask for an instruction that takes a board description in two XMM registers, and replaces it with the best move and its score...

Then Intel should hire me, because, I could build a model train system that would do what I proposed and the trains would all arrive simultaineously at their destination stations with out collisions --unless a school bus just happens to get in the way.